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ST
Sitronix
1. INTRODUCTION
ST7531
65K Color Dot Matrix LCD Controller/Driver
The ST7531 is a driver & controller LSI for 65K color graphic dot-matrix liquid crystal display systems. It generates 256 Segment and 160 Common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface (SPI), 8-bit/16-bit parallel or IIC display data and stores in an on-chip display data RAM. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
Driver Output Circuits
-256 segment outputs / 160 common outputs -Maximum resolution is 170(SPRD) x 160.
On-chip Low Power Analog Circuit
- On-chip oscillator circuit - Voltage converter (x2, x3, x4, x5, x6, x7, x8) - Voltage regulator - Voltage follower (LCD bias: 1/5, 1/7, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14)
Applicable Duty Ratios
- Various partial display - Partial window moving & data scrolling
Microprocessor Interface
- 8/16-bit parallel bi-directional interface with 6800-series or 8080-series -4-line serial interface (write only) -9 bit 3-line serial interface (write only)
Operating Voltage Range
- Supply voltage (VDD, VDD1, VDD2, VDD3, VDD4, VDD5): 2.4 to 3.3V - LCD driving voltage (VLCD = V0 - VSS): 3.76 to 18.0 V
Temperature Gradient Coefficient
- -0.130%/ +/-10%
On-chip Display Data RAM
- Capacity : 160 x 256 x 5bit = 204800bits (Max)
LCD driving voltage (EEPROM)
- To store contrast adjustment value for better display
Package Type
- Application for COG
ST7531
6800, 8080, 4-Line, 3-Line interface
Ver 1.8
1/84
2006/9/18
ST7531
3. SPRD- B Mode Color Filter ( [M1,M0] = [1,0] )
The ST7531 applies SPRD- B mode color filter, which is shown in the figures below. Note: When you use SPRD B mode, you must use this color filter placement. You can not change COM and SEG ITO layout direction.
Ver 1.8
2/85
2006/9/18
ST7531
4. Pad Arrangement
Chip Size :
16.550mm x 1.525mm
Pad pitch :
Com, Seg pad pitch: 43m IO pad pitch: 110m Test pin pad pitch: 75m
Pad size :
Com, Seg pad size: Pad No1~362 : 25m (X) x 96m (Y) Pad No363~390 : 96m (X) x 25m (Y) Pad No544~571 : 96m (X) x 25m (Y) IO pad pad size: 90m (X) x 40m (Y) Test pin pad size: 55m (X) x 40m (Y)
Bump Height: 17m Chip Thickness: 635m
Ver 1.8
3/85
2006/9/18
ST7531
5. Pad Center Coordinates
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Ver 1.8 PIN Name COM[28] COM[29] COM[30] COM[31] COM[32] COM[33] COM[34] COM[35] COM[36] COM[37] COM[38] COM[39] COM[40] COM[41] COM[42] COM[43] COM[44] COM[45] COM[46] COM[47] COM[48] COM[49] COM[50] COM[51] COM[52] COM[53] COM[54] COM[55] COM[56] COM[57] COM[58] COM[59] COM[60] COM[61] COM[62] COM[63] COM[64] COM[65] X 7917 7874 7831 7788 7745 7702 7659 7616 7573 7531 7487 7444 7401 7358 7315 7272 7229 7186 7143 7100 7057 7014 6971 6928 6885 6842 6799 6756 6713 6670 6627 6584 6541 6498 6455 6412 6369 6326 Y 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 4/85 PAD No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 PIN Name COM[66] COM[67] COM[68] COM[69] COM[70] COM[71] COM[72] COM[73] COM[74] COM[75] COM[76] COM[77] COM[78] COM[79] (NC) (NC) SEG[255] SEG[254] SEG[253] SEG[252] SEG[251] SEG[250] SEG[249] SEG[248] SEG[247] SEG[246] SEG[245] SEG[244] SEG[243] SEG[242] SEG[241] SEG[240] SEG[239] SEG[238] SEG[237] SEG[236] SEG[235] SEG[234] X 6283 6240 6197 6154 6111 6068 6025 5982 5939 5896 5853 5810 5767 5724 5526 5482 5440 5396 5354 5310 5268 5224 5182 5138 5096 5052 5010 4966 4924 4880 4838 4794 4752 4708 4666 4622 4580 4536 Y 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683
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ST7531
PAD No. 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 Ver 1.8 PIN Name SEG[233] SEG[232] SEG[231] SEG[230] SEG[229] SEG[228] SEG[227] SEG[226] SEG[225] SEG[224] SEG[223] SEG[222] SEG[221] SEG[220] SEG[219] SEG[218] SEG[217] SEG[216] SEG[215] SEG[214] SEG[213] SEG[212] SEG[211] SEG[210] SEG[209] SEG[208] SEG[207] SEG[206] SEG[205] SEG[204] SEG[203] SEG[202] SEG[201] SEG[200] SEG[199] SEG[198] SEG[197] SEG[196] SEG[195] X 4494 4450 4408 4364 4322 4278 4236 4192 4150 4106 4064 4020 3978 3934 3892 3848 3806 3762 3720 3676 3634 3590 3548 3504 3462 3418 3376 3332 3290 3246 3204 3160 3118 3074 3032 2988 2946 2902 2860 Y 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 5/85 PAD No. 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 PIN Name SEG[194] SEG[193] SEG[192] SEG[191] SEG[190] SEG[189] SEG[188] SEG[187] SEG[186] SEG[185] SEG[184] SEG[183] SEG[182] SEG[181] SEG[180] SEG[179] SEG[178] SEG[177] SEG[176] SEG[175] SEG[174] SEG[173] SEG[172] SEG[171] SEG[170] SEG[169] SEG[168] SEG[167] SEG[166] SEG[165] SEG[164] SEG[163] SEG[162] SEG[161] SEG[160] SEG[159] SEG[158] SEG[157] SEG[156] X 2816 2774 2730 2688 2644 2602 2558 2516 2472 2430 2386 2344 2300 2258 2214 2172 2128 2086 2042 2000 1956 1914 1870 1828 1784 1742 1698 1656 1612 1570 1526 1484 1440 1398 1354 1312 1268 1226 1182 Y 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683
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ST7531
PAD No. 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 Ver 1.8 PIN Name SEG[155] SEG[154] SEG[153] SEG[152] SEG[151] SEG[150] SEG[149] SEG[148] SEG[147] SEG[146] SEG[145] SEG[144] SEG[143] SEG[142] SEG[141] SEG[140] SEG[139] SEG[138] SEG[137] SEG[136] SEG[135] SEG[134] SEG[133] SEG[132] SEG[131] SEG[130] SEG[129] SEG[128] SEG[127] SEG[126] SEG[125] SEG[124] SEG[123] SEG[122] SEG[121] SEG[120] SEG[119] SEG[118] SEG[117] X 1140 1096 1054 1010 968 924 882 838 796 752 710 666 624 580 538 494 452 408 366 322 280 236 194 150 108 64 22 -22 -64 -108 -150 -194 -236 -280 -322 -366 -408 -452 -494 Y 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 6/85 PAD No. 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 PIN Name SEG[116] SEG[115] SEG[114] SEG[113] SEG[112] SEG[111] SEG[110] SEG[109] SEG[108] SEG[107] SEG[106] SEG[105] SEG[104] SEG[103] SEG[102] SEG[101] SEG[100] SEG[99] SEG[98] SEG[97] SEG[96] SEG[95] SEG[94] SEG[93] SEG[92] SEG[91] SEG[90] SEG[89] SEG[88] SEG[87] SEG[86] SEG[85] SEG[84] SEG[83] SEG[82] SEG[81] SEG[80] SEG[79] SEG[78] X -538 -580 -624 -666 -710 -752 -796 -838 -882 -924 -968 -1010 -1054 -1096 -1140 -1182 -1226 -1268 -1312 -1354 -1398 -1440 -1484 -1526 -1570 -1612 -1656 -1698 -1742 -1784 -1828 -1870 -1914 -1956 -2000 -2042 -2086 -2128 -2172 Y 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683
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ST7531
PAD No. 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 Ver 1.8 PIN Name SEG[77] SEG[76] SEG[75] SEG[74] SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] X -2214 -2258 -2300 -2344 -2386 -2430 -2472 -2516 -2558 -2602 -2644 -2688 -2730 -2774 -2816 -2860 -2902 -2946 -2988 -3032 -3074 -3118 -3160 -3204 -3246 -3290 -3332 -3376 -3418 -3462 -3504 -3548 -3590 -3634 -3676 -3720 -3762 -3806 -3848 Y 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 7/85 PAD No. 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 PIN Name SEG[38] SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] SEG[1] SEG[0] X -3892 -3934 -3978 -4020 -4064 -4106 -4150 -4192 -4236 -4278 -4322 -4364 -4408 -4450 -4494 -4536 -4580 -4622 -4666 -4708 -4752 -4794 -4838 -4880 -4924 -4966 -5010 -5052 -5096 -5138 -5182 -5224 -5268 -5310 -5354 -5396 -5440 -5482 -5526 Y 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683
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ST7531
PAD No. 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 Ver 1.8 PIN Name COM[80] COM[81] COM[82] COM[83] COM[84] COM[85] COM[86] COM[87] COM[88] COM[89] COM[90] COM[91] COM[92] COM[93] COM[94] COM[95] COM[96] COM[97] COM[98] COM[99] COM[100] COM[101] COM[102] COM[103] COM[104] COM[105] COM[106] COM[107] COM[108] COM[109] COM[110] COM[111] COM[112] COM[113] COM[114] COM[115] COM[116] COM[117] COM[118] X -5724 -5767 -5810 -5853 -5896 -5939 -5982 -6025 -6068 -6111 -6154 -6197 -6240 -6283 -6326 -6369 -6412 -6455 -6498 -6541 -6584 -6627 -6670 -6713 -6756 -6799 -6842 -6885 -6928 -6971 -7014 -7057 -7100 -7143 -7186 -7229 -7272 -7315 -7358 Y 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 683 8/85 PAD No. 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 PIN Name COM[119] COM[120] COM[121] COM[122] COM[123] COM[124] COM[125] COM[126] COM[127] COM[128] COM[129] COM[130] COM[131] COM[132] COM[133] COM[134] COM[135] COM[136] COM[137] COM[138] COM[139] COM[140] COM[141] COM[142] COM[143] COM[144] COM[145] COM[146] COM[147] COM[148] COM[149] COM[150] COM[151] COM[152] COM[153] COM[154] COM[155] COM[156] COM[157] X -7401 -7444 -7487 -7531 -7573 -7616 -7659 -7702 -7745 -7788 -7831 -7874 -7917 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 -8196 Y 683 683 683 683 683 683 683 683 683 683 683 683 683 661 618 575 532 489 446 403 360 317 274 231 188 145 102 59 16 -27 -70 -113 -156 -199 -242 -285 -328 -371 -414
2006/9/18
ST7531
PAD No. 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 Ver 1.8 PIN Name COM[158] COM[159] T[10] T[9] T[8] T[7] T[6] T[5] T[4] T[3] T[2] T[1] T[0] VSS VSS VSS VSS VSS4 VSS4 VSS1 VSS1 VDD1 VDD1 VDD VDD VDD VDD VDD VDD CL CLS VSS VDD A0 RW_WR VSS VDD D0 D1 X -8196 -8196 -8197 -8122 -8047 -7972 -7897 -7822 -7747 -7672 -7597 -7522 -7447 -7355 -7245 -7135 -7025 -6915 -6805 -6695 -6585 -6475 -6365 -6255 -6145 -6035 -5925 -5815 -5705 -5595 -5485 -5375 -5265 -5155 -5045 -4935 -4825 -4715 -4605 Y -457 -500 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 9/85 PAD No. 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 PIN Name D2 D3 D4 D5 D6 D7 VSS VDD D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RST VSS VDD M0 M1 IF1 IF2 IF3 VSS VDD SI SCL XCS VDD VDD VDD VDD VDD VDD VDD1 X -4495 -4385 -4275 -4165 -4055 -3945 -3835 -3725 -3615 -3505 -3395 -3285 -3175 -3065 -2955 -2845 -2735 -2625 -2515 -2405 -2295 -2185 -2075 -1965 -1855 -1745 -1635 -1525 -1415 -1305 -1195 -1085 -975 -865 -755 -645 -535 -425 -315 Y -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712
2006/9/18
ST7531
PAD No. 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 Ver 1.8 PIN Name VDD1 VSS1 VSS1 VSS VSS VSS VSS VSS VSS VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS4 VSS4 VDD4 VDD4 VDD3 VDD3 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD5 VDD5 VDD5 X -205 -95 15 125 235 345 455 565 675 785 895 1005 1115 1225 1335 1445 1555 1665 1775 1885 1995 2105 2215 2325 2435 2545 2655 2765 2875 2985 3095 3205 3315 3425 3535 3645 3755 3865 3975 Y -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 10/85 PAD No. 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 PIN Name VDD5 TCAP C7P C1N C5P C3P C1N C1P C2P C2N C4P C2N C6P VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VREF V4 V3 V2 V1 V0OUT V0OUT V0OUT V0OUT V0IN V0IN V0IN V0IN COM[0] X 4085 4195 4305 4415 4525 4635 4745 4855 4965 5075 5185 5295 5405 5515 5625 5735 5845 5955 6065 6175 6285 6395 6505 6615 6725 6835 6945 7055 7165 7275 7385 7495 7605 7715 7825 7935 8045 8155 8196 Y -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -712 -500
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PAD No. 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 PIN Name COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] X 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 8196 Y -457 -414 -371 -328 -285 -242 -199 -156 -113 -70 -27 16 59 102 145 188 231 274 317 360 403 446 489 532 575 618 661
Ver 1.8
11/85
2006/9/18
ST7531
f. BLOCK DIAGRAM
SEG0 TO SEG255 COM0 TO COM159
VDD1 VDD
V0 In V1 V2 V3 V4 COMMON DRIVERS
M0 M1
SEGMENT DRIVERS
VSS
DATA LATCHES V/F Circuit
COMMON OUTPUT CONTROLLER CIRCUIT
V0 out VREF
V/R Circuit
FRC/PWM FUNCTION CIRCUIT
CLS
OSCILLATOR
CL
Cap1P Cap1N Cap2P Cap2N Cap3P Cap4P Cap5P Cap6P Cap7P
DISPLAY DATA RAM (DDRAM) [160X256X5] S P RD V/C Circuit ADDRESS COUNTER
TIMING GENERATOR DISPLAY ADDRESS COUNTER
VDD5 VDD4 VDD3 VDD2 VLCDin VLCDout
DATA REGISTER BUS HOLDER
INSTRUCTION REGISTER INSTRUCTION DECODER
VSS1 VSS4
MPU INTERFACE(PARALLEL & SERIAL)
A0 XCS RST
E_RD
RW_WR
IF3 IF2 IF1
SCL
SI
D0 to D15
Ver 1.8
12/85
2006/9/18
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7. PIN DESCRIPTION
7.1 POWER SUPPLY
Name VDD VDD1 VDD2 VDD3 VDD4 VDD5 VSS VSS1 VSS4 I/O Supply Power supply for logic circuit Supply Power supply for OSC circuit Supply Power supply for Booster Circuit Supply Power supply for LCD Description
Supply Ground. Ground system should be connected together. If the internal voltage generator is used, the VLCDIN & VLCDOUT must be connected together. If an external supply is used, this pin must be left open. An external LCD supply voltage can be supplied using the VLCDIN pad. In this case, VLCDOUT has to be left Supply open, and the internal voltage generator has to be programmed to zero. (SET register VB=0) LCD driver supply voltages V0In & V0out should be connected together in FPC area. Voltages should have the following relationship: V0 V1 V2 V3 V4 VSS Supply When the internal power circuit is active, these voltages are generated as the following table according to the state of LCD bias. LCD bias V1 V2 V3 V4 1/N bias NOTE: N = 5 to 14 (N-1) / N x V0 (N-2) / N x V0 (2/N) x V0 (1/N) x V0
VLCDOUT Supply VLCDIN
V0In V0out V1 V2 V3 V4
7.2 LCD DRIVER SUPPLY
Name VREF CLS CL I/O O I I/O Description Reference voltage output for monitor only. Leave it open. When using internal clock oscillator, connect CLS to VDD. When using external clock oscillator, connect CLS to VSS. When using internal clock oscillator, it is the output of oscillator. When using external clock oscillator, it is the input of oscillator.
7.3 SYSTEM CONTROL
Name TCAP T[0]~T[10] I/O O --Description Test pin. Leave it open. Test pin. Leave it open.
Ver 1.8
13/85
2006/9/18
ST7531
7.4 MICROPROCESSOR INTERFACE
Name M0, M1 RST XCS I/O I I I Description M0 must be fixed to Vss. M1 must fixed to VDD. This pin is reserved for internal setting. Reset input pin When RST is "L", initialization is executed. Chip select input pins Data/instruction I/O is enabled only when XCS is "L". When chip select is non-active, DB0 to DB15 may be high impedance. Parallel / Serial data input select input IF1 IF2 IF3 MPU interface type H H H L L L H H L H L L H L L H H L 80 series 16-bit parallel 80 series 8-bit parallel 68 series 16-bit parallel 68 series 8-bit parallel 9-bit serial (3 line) 8-bit serial (4 line)
IF[3:1]
I
A0
I
Register select input pin - A0 = "H": DB0 to DB15 or SI are display data - A0 = "L": DB0 to DB15 or SI are control data Read / Write execution control pin MPU type RW_WR 6800-series RW
Description
RW_WR
I
8080-series
/WR
Read / Write control input pin RW = "H" : read RW = "L" : write Write enable clock input pin The data on DB0 to DB15 are latched at the rising edge of the /WR signal. Description Read / Write control input pin - RW = "H": When E is "H", DB0 to DB15 are in an output status. - RW = "L": The data on DB0 to DB15 are latched at the falling edge of the E signal. Read enable clock input pin When /RD is "L", DB0 to DB15 are in an output status.
Read / Write execution control pin MPU Type E_RD
E_RD
I
6800-series
E
8080-series
/RD
D15 to D0
I/O
They connect to the standard 8-bit or 16-bit MPU bus via the 8/16 -bit bi-directional bus. When the following interface is selected and the XCS pin is high, the following pins become high impedance, which should be fixed to VDD or VSS. 1. 8-bit parallel: D15-D8 are in the state of high impedance 2. Serial interface: D15-D0 are in the state of high impedance
SI SCL
I I
This pin is used to input serial data when the serial interface is selected. (3 line and 4 line) This pin is used to input serial clock when the serial interface is selected. The data is latched at the rising edge. (3 line and 4 line)
NOTE: Microprocessor interface pins should not be floating in any operation mode.
Ver 1.8
14/85
2006/9/18
ST7531
7.5 LCD DRIVER OUTPUTS
Name I/O Description LCD segment driver outputs The display data and the M signal control the output voltage of segment driver. Segment driver output voltage Display data M (Internal) Normal display Reverse display H H L L H L H L V0 VSS V2 V3 VSS V2 V3 V0 VSS VSS
SEG0 to SEG255
O
COM0 to COM159
Power save mode LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver. Scan data M (Internal) Common driver output voltage O H H L L Power save mode H L H L VSS V0 V1 V4 VSS
Ver 1.8
15/85
2006/9/18
ST7531
8. FUNCTIONAL DESCRIPTION
8.1 MICROPROCESSOR INTERFACE
Chip Select Input
The XCS pin is for chip selection. The ST7531 can function with an MPU when XCS is "L". In case of serial interface, the internal shift register and the counter are reset.
8.1.1 Selecting Parallel / Serial Interface
ST7531 has six types of interface with an MPU, which are four parallel and three serial interfaces. This parallel or serial interface is determined by IF pin as shown in table 8.1.1.
Table 8.1.1 Parallel / Serial Interface Mode
IF1 IF2 IF3 Interface type H H H 80 serial 16-bit parallel H H L 80 serial 8-bit parallel H L L 68 serial 16-bit parallel L H H 68 serial 8-bit parallel L L H 9-bit SPI mode (3 line) L L L 8-bit SPI mode (4 line) XCS XCS XCS XCS XCS XCS XCS A0 A0 A0 A0 A0 -A0 /RD(E) /WR(R/W) D15 to D8 /RD /WR D15 to D8 /RD /WR -E R/W D15 to D8 E R/W -------D7 to D0 SI D7 to D0 -D7 to D0 -D7 to D0 -D7 to D0 -SI SI SCL ----SCL SCL ACK -------
Note: "--" means "disabled" in pins A0, E_RD, and RW_WR, and "high impedance" in pins DB0 to DB15.
8.1.2 8- or 16-bit Parallel Interface
The ST7531 identifies the type of the data bus signals according to the combination of A0, /RD (E) and /WR (W/R) as shown in table 8.1.2.
Table 8.1.2 Parallel Data Transfer
Common A0 H H L L H L H L 6800-series R/W E H H H H /RD L H L H 8080-series /WR H L H L Description Display data read out Display data write Register status read Writes to internal register (instruction)
Relation between Data Bus and Gradation Data ST7531 offers the dithered 65K, dithered 262K, and dithered 16M color display. When using 65K, 262K, and 16M color, you can specify color for each of R, G, B using the palette function. (1) 65K color display 1. 8-bit mode D7 D6 D5 D4 D3 D2 D1 D0 R R R R R G G G 1st write G G G B B B B B 2nd write A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
2. 16-bit mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R R R R R G GGGGGBBBBB Data is acquired through the operation of writing signal, and then written to the display RAM.
Ver 1.8
16/85
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ST7531
(2) 262K color display 1. 8-bit mode D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R X X 1st write G G G G G G X X 2nd write B B B B B B X X 3rd write A single pixel of data is read after the third write operation as shown, and it is written in the display RAM.
2. 16 bit mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R B R B R B R B R B R B X X G G G G G G X X 1st write X X X X X X X X X X 2nd write
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM. "XXXX" are dummy bits, which are ignored for display. (3) 16M color display 1. 8-bit mode D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R 1st write G G G G G G G G 2nd write B B B B B B B B 3rd write A single pixel of data is read after the third write operation as shown, and it is written in the display RAM.
2. 16 bit mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R B R B R B R B R B R B R R G G G G G G G G 1st write B B X X X X X X X X 2nd write
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
8.1.3 8-bit (4 line) and 9-bit (3 line) Serial Interface
The 8-bit serial interface uses four pins XCS, SI, SCL, and A0 to enter commands and data. Meanwhile, the 9-bit serial interface uses three pins XCS, SI and SCL for the same purpose. Data read is not available in the serial interface. The entered data must be 8 bits. Refer to the following chart for entering commands, parameters or gray-scale data. The relation between gray-scale data and data bus in the serial input is the same as that in the 8-bit parallel interface mode at every gradation.
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ST7531
(1) 8-bit serial interface (4 line) When entering data (parameters): A0= HIGH at the rising edge of the 8 SCL.
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When entering command: A0= LOW at the rising edge of the 8 SCL
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(2) 9-bit serial interface (3 line) When entering data (parameters): SI= HIGH at the rising edge of the 1 SCL.
st
When entering command: SI= LOW at the rising edge of the 1 SCL.
st
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18/85
2006/9/18
ST7531
If XCS is set to HIGH while the 8 bits from D7 to D0 are entered, the data concerned is invalid. Before entering succeeding sets of data, you must correctly input the data concerned again. In order to avoid data transfer error due to incoming noise, it is recommended to set XCS at HIGH on byte basis to initialize the serial-to-parallel conversion counter and the register. When executing the command RAMWR, set XCS to HIGH after writing the last address (after starting the 9 pulse in case of 9-bit serial input or after starting the 8 pulse in case of 8-bit serial input).
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Ver 1.8
19/85
2006/9/18
ST7531
8.2 ACCESS TO DDRAM AND INTERNAL REGISTERS
Since ST7531 access from MPU by pipeline processing via the bus holder attached to the internal that requires only the cycle time but no waiting time, it can achieves high-speed data transfer. For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the DDRAM before the succeeding write cycle start. When MPU reads data from the DDRAM, the first read cycle is dummy and the data read in the dummy cycle is held by the bus holder, and then it read from the bus holder to the system bus in the succeeding read cycle. Fig. 8.2.1 illustrates these relations.
MPU signal
Write Operation
A0 /WR
DATA Internal signals /WR BUS HOLDER COLUMN ADDRESS
N
D(N)
D(N+1) D(N+2)
D(N+3)
N
D(N) N
D(N+1) N+1
D(N+2) N+2
D(N+3) N+3
MPU signal
Read Operation
A0 /WR /RD DATA Internal signals /WR /RD N Dummy D(N) D(N+1)
BUS HOLDER COLUMN ADDRESS
N N
D(N) D(N)
D(N+1) D(N+1)
D(N+2) D(N+2)
Fig 8.2.1
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ST7531
8.3 DISPLAY DATA RAM (DDRAM)
8.3.1 DDRAM
It is 160 X 256 X 5 bits capacity RAM prepared for storing dot data. You can access a desired bit by specifying the LINE address and column address. Since the display data from MCU D7 to D0 and D15 to D8 correspond to one or two pixels, data transfer related restrictions are reduced, and the display would be flexible. The RAM on ST7531 is separated to a block per 4 lines to allow the display system to process data on the block basis. The reading and writing RAM operations of MPU are performed via the I/O buffer circuit. Reading of the RAM for the liquid crystal drive is controlled from another separate circuit. Refer to the following memory map for the RAM configuration.
Ver 1.8
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ST7531
Memory Map (using the 32 gray-scale dithered 65Kcolor, 8-bit mode) RGB alignment (Command of data control CLR = 0) Column 0 1 2 3 G B R G B D2'1,(0+1)/2 D1'1,(0+1)/2 D0'1,(0+1)/2 D7'2,(0+1)/2 D6'2,(0+1)/2 D4'2,1 D3'2,1 D2'2,1 D1'2,1 D0'2,1 D7'1,2 D6'1,2 D5'1,2 D4'1,2 D3'1,2 D2'1,(2+3)/2 D1'1,(2+3)/2 D0'1,(2+3)/2 D7'2,(2+3)/2 D6'2,(2+3)/2 D4'2,3 D3'2,3 D2'2,3 D1'2,3 D0'2,3
LCD read direction
CI = 0 Color Data Line
168 R D7'1,168 D6'1,168 D5'1,168 D4'1,168 D3'1,168 G
169 B D4'2,169 D3'2,169 D2'2,169 D1'2,169 D0'2,169
R D7'1,0 D6'1,0 D5'1,0 D4'1,0 D3'1,0
D2'1,(168+169)/2 D1'1,(168+169)/2 D0'1,(168+169)/2 D7'2,(168+169)/2 D6'2,(168+169)/2 1 0 G D2'1,(0+1)/2 D1'1,(0+1)/2 D0'1,(0+1)/2 D7'2,(0+1)/2 D6'2,(0+1)/2
Block
0
1
2
CI = 1 169 168 Color B G R Data Line D4'2,169 D2'1,(168+169)/2 D7'1,168 LI = LI = D3'2,169 D1'1,(168+169)/2 D6'1,168 D2'2,169 D0'1,(168+169)/2 D5'1,168 0 1 D1'2,169 D7'2,(168+169)/2 D4'1,168 D0'2,169 D6'2,(168+169)/2 D3'1,168 0 159 1 158 2 157 3 156 4 155 5 154 6 153 7 152 8 151 9 150 152 153 154 155 156 157 158 159 7 6 5 4 3 2 1 0 0 1 2
167 166 B G R D2'1,167 D4'2,(166+167)/2 D7'1,166 D1'1,167 D3'2,(166+167)/2 D6'1,166 D0'1,167 D2'2,(166+167)/2 D5'1,166 D7'2,167 D1'2,(166+167)/2 D4'1,166 D6'2,167 D0'2,(166+167)/2 D3'1,166
B D4'2,1 D3'2,1 D2'2,1 D1'2,1 D0'2,1
R D7'1,0 D6'1,0 D5'1,0 D4'1,0 D3'1,0
38
39
SEGout
3
4
5
252
253
254
You can change position of R and B with DATACTRL command.
Dki,j is the k data bit of the i write for pixel j, Dk'i,j is the k data bit of the i write for pixel j after dithering or truncating, and Dk'i,(j+(j+1))/2 is the average value of the k data bit of the i write for pixel j and pixel j+1after dithering or truncating.
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Ver 1.8
22/85
2006/9/18
ST7531
Memory Map (using the 32 gray-scale, dithered 65K color, 16-bit mode) RGB alignment (Command of data control CLR = 0) Column 0 1 2 3 G B R G B D10'(0+1)/2 D9'(0+1)/2 D8'(0+1)/2 D7'(0+1)/2 D6'(0+1)/2 D4'1 D3'1 D2'1 D1'1 D0'1 D15'2 D14'2 D13'2 D12'2 D11'2 D10'(2+3)/2 D9'(2+3)/2 D8'(2+3)/2 D7'(2+3)/2 D6'(2+3)/2 D4'3 D3'3 D2'3 D1'3 D0'3
LCD read direction
CI = 0 Color Data Line
168 R D15'168 D14'168 D13'168 D12'168 D11'168 G
169 B D4'169 D3'169 D2'169 D1'169 D0'169
R D15'0 D14'0 D13'0 D12'0 D11'0
D10'(168+169)/2 D9'(168+169)/2 D8'(168+169)/2 D7'(168+169)/2 D6'(168+169)/2 1 0 G D10'(0+1)/2 D9'(0+1)/2 D8'(0+1)/2 D7'(0+1)/2 D6'(0+1)/2
Block
0
1
2
CI = 1 169 168 Color B G R Data Line D4'169 D10'(168+169)/2 D15'168 LI = LI = D3'169 D9'(168+169)/2 D14'168 D2'169 D8'(168+169)/2 D13'168 0 1 D1'169 D7'(168+169)/2 D12'168 D0'169 D6'(168+169)/2 D11'168 0 159 1 158 2 157 3 156 4 155 5 154 6 153 7 152 8 151 9 150 152 153 154 155 156 157 158 159 7 6 5 4 3 2 1 0 0 1 2
167 166 B G D4'167 D10'(166+167)/2 D15'166 D3'167 D9'(166+167)/2 D14'166 D2'167 D8'(166+167)/2 D13'166 D1'167 D7'(166+167)/2 D12'166 D0'167 D6'(166+167)/2 D11'166
B D4'1 D3'1 D2'1 D1'1 D0'1
R D15'0 D14'0 D13'0 D12'0 D11'0
38
39
SEGout
3
4
5
252
253
254
You can change position of R and B with DATACTRL command.
Dk,j is the k data bit of pixel j, Dk',j is the k data bit of pixel j after dithering or truncating, and Dk',(j+(j+1))/2 is the average value of the k data bit of pixel j and pixel j+1 after dithering or truncating.
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Ver 1.8
23/85
2006/9/18
ST7531
Memory Map (using the 32 gray-scale, dithered 262K/16Mcolor, 8-bit mode) RGB alignment (Command of data control CLR = 0) Column 0 1 2 3 G B R G B D7'2,(0+1)/2 D6'2,(0+1)/2 D5'2,(0+1)/2 D4'2,(0+1)/2 D3'2,(0+1)/2 D7'3,1 D6'3,1 D5'3,1 D4'3,1 D3'3,1 D7'1,2 D6'1,2 D5'1,2 D4'1,2 D3'1,2 D7'2,(2+3)/2 D6'2,(2+3)/2 D5'2,(2+3)/2 D4'2,(2+3)/2 D3'2,(2+3)/2 D7'3,3 D6'3,3 D5'3,3 D4'3,3 D3'3,3
LCD CI = 0 read Color direction Data Line
168 R D7'1,168 D6'1,168 D5'1,168 D4'1,168 D3'1,168 G
169 B D7'3,169 D6'3,169 D5'3,169 D4'3,169 D3'3,169
R D7'1,0 D6'1,0 D5'1,0 D4'1,0 D3'1,0
D7'2,(168+169)/2 D6'2,(168+169)/2 D5'2,(168+169)/2 D4'2,(168+169)/2 D3'2,(168+169)/2 1 0 G D7'2,(0+1)/2 D6'2,(0+1)/2 D5'2,(0+1)/2 D4'2,(0+1)/2 D3'2,(0+1)/2
Block
0
1
2
CI = 1 169 168 167 166 Color B G R B G Data Line D7'3,169 D7'2,(168+169)/2 D7'1,168 D7'3,167 D7'2,(166+167)/2 D7'1,166 LI = LI = D6'3,169 D6'2,(168+169)/2 D6'1,168 D6'3,167 D6'2,(166+167)/2 D6'1,166 D5'3,169 D5'2,(168+169)/2 D5'1,168 D5'3,167 D5'2,(166+167)/2 D5'1,166 0 1 D4'3,169 D4'2,(168+169)/2 D4'1,168 D4'3,167 D4'2,(166+167)/2 D4'1,166 D3'3,169 D3'2,(168+169)/2 D3'1,168 D3'3,167 D3'2,(166+167)/2 D3'1,166 0 159 1 158 2 157 3 156 4 155 5 154 6 153 7 152 8 151 9 150 152 153 154 155 156 157 158 159 7 6 5 4 3 2 1 0 0 1 2 3 4 5
B D7'3,1 D6'3,1 D5'3,1 D4'3,1 D3'3,1
R D7'1,0 D6'1,0 D5'1,0 D4'1,0 D3'1,0
38
39
SEGout
252
253
254
You can change position of R and B with DATACTRL command.
Dki,j is the k data bit of the i write for pixel j, Dk'i,j is the k data bit of the i write for pixel j after dithering or truncating, and Dk'i,(j+(j+1))/2 is the average value of the k data bit of the i write for pixel j and pixel j+1after dithering or truncating.
th th
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Ver 1.8
24/85
2006/9/18
ST7531
Memory Map (using the 32 gray-scale, dithered 262K/16M color, 16-bit mode) RGB alignment (Command of data control CLR = 0) Column 1 2 3 G B R G B D7'1,(0+1)/2 D6'1,(0+1)/2 D5'1,(0+1)/2 D4'1,(0+1)/2 D3'1,(0+1)/2 D15'2,1 D14'2,1 D13'2,1 D12'2,1 D11'2,1 D15'1,2 D14'1,2 D13'1,2 D12'1,2 D11'1,2 D7'1,(2+3)/2 D6'1,(2+3)/2 D5'1,(2+3)/2 D4'1,(2+3)/2 D3'1,(2+3)/2 D15'2,3 D14'2,3 D13'2,3 D12'2,3 D11'2,3
LCD CI = 0 read Color direction Data Line
0 R D15'1,0 D14'1,0 D13'1,0 D12'1,0 D11'1,0
168 R G
169 B D15'2,169 D14'2,169 D13'2,169 D12'2,169 D11'2,169
D15'1,168 D7'1,(168+169)/2 D14'1,168 D6'1,(168+169)/2 D13'1,168 D5'1,(168+169)/2 D12'1,168 D4'1,(168+169)/2 D11'1,168 D3'1,(168+169)/2 1 B D15'2,1 D14'2,1 D13'2,1 D12'2,1 D11'2,1 G D7'1,(0+1)/2 D6'1,(0+1)/2 D5'1,(0+1)/2 D4'1,(0+1)/2 D3'1,(0+1)/2 0
Block
CI = 1 Color Data Line LI = LI = 01 0 1 2 3 4 5 6 7 8 9 152 153 154 155 156 157 158 159 159 158 157 156 155 154 153 152 151 150 7 6 5 4 3 2 1 0
169 168 B G R D15'2,169 D7'1,(168+169)/2 D15'1,168 D14'2,169 D6'1,(168+169)/2 D14'1,168 D13'2,169 D5'1,(168+169)/2 D13'1,168 D12'2,169 D4'1,(168+169)/2 D12'1,168 D11'2,169 D3'1,(168+169)/2 D11'1,168
167 166 B G R D15'2,167 D7'1,(166+167)/2 D15'1,166 D14'2,167 D6'1,(166+167)/2 D14'1,166 D13'2,167 D5'1,(166+167)/2 D13'1,166 D12'2,167 D4'1,(166+167)/2 D12'1,166 D11'2,167 D3'1,(166+167)/2 D11'1,166
R D15'1,0 D14'1,0 D13'1,0 D12'1,0 D11'1,0
0
1
2
38
39
SEGout
0
1
2
3
4
5
252
253
254
You can change position of R and B with DATACTRL command.
Dki,j is the k data bit of the i write for pixel j, Dk'i,j is the k data bit of the i write for pixel j after dithering or truncating, and Dk'i,(j+(j+1))/2 is the average value of the k data bit of the i write for pixel j and pixel j+1after dithering or truncating.
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Ver 1.8
25/85
2006/9/18
ST7531
8.3.2 Line Address Control Circuit
This circuit is to control the address in the line direction when MPU accesses the DDRAM or read the DDRAM to display image on the LCD. You can specify a range of the line address with line address set command. When the line-direction scan is specified with DATACTRL command and the address are increased from the start up to the end line, the column address is increased by 1 and the line address returns to the start line. The DDRAM supports up to 160 lines, and thus the total line becomes 160. In the READ operation, as the end line is reached, the column address is automatically increased by 1 and the line address returns to the start line. Users may inverse the correspondence between the DDRAM address and common output via the address normal/inverse parameter of DATACTRL command.
8.3.3 Column Address Control Circuit
This circuit is to control the address in the column direction when MPU accesses the DDRAM. You can specify a range of the column address with column address set command. When the column-direction scan is specified with DATACTRL command and the address are increased from the start up to the end line, the line address is increased by 1 and the column address returns to the start column. In the READ operation, the column address is also automatically increased by 1 and returns to the start line as the end column is reached. Just like the line address control circuit, users may inverse the correspondence between the DDRAM column address and segment output via the column address normal/inverse parameter of DATACTRL command. This arrangement makes the chip layout on the LCD module flexible.
8.3.4 I/O Buffer Circuit
It is the bi-directional buffer when MPU reads or writes the DDRAM. Since the READ or WRITE operation of MPU to DDRAM is performed independently from data output to the display data latch circuit, asynchronous access to the DDRAM while the LCD is turned on does not cause troubles such as flicking of the display images.
8.3.5 Block Address Circuit
The circuit associates lines on DDRAM with COM output. ST7531 processes signals for the liquid crystal display on 4-line basis. Thus, when specifying a specific area in the area of scroll display or partial display, you must designate it in block.
8.3.6 Display Data Latch Circuit
This circuit is used to temporarily hold display data to be output from the DDRAM to the SEG decoder circuit. Since display normal/inverse and display on/off commands are used to control data in the latch circuit alone, they do not modify data in the DDRAM.
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ST7531
8.4 Area Scroll Display
The user may scroll the display screen partially in any one of the following four scroll patterns via AREA SCROLL SET and SCROLL START SET commands.
Center mode
Top mode
Bottom mode
Whole mode
Fixed area
Scrolled area
8.5 Partial Display
The user may turn on the partial display (division by line) of the screen via PARTIAL IN command. This mode consumes less current than the whole screen display and is suitable for the equipment in the standby state.
: Display area (partial display area)
: Non-display area
If the partial display region is out of the maximum display range, it will be no operation.
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-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Figure 8.5.1.Reference Example for Partial Display
Figure 8.5.2.Partial Display
Figure 8.5.3.Moving Display
Ver 1.8
28/85
2006/9/18
ST7531
8.6 Gray-Scale Display
ST7531 incorporates a 2 FRC & 31 PWM function circuit to display a 32 gray-scale display.
8.7 Oscillation Circuit
This is an on-chip oscillator without external resistor. When the internal oscillator is used, this pin must connect to VDD; when the external oscillator is used, this pin could be an input pin. This oscillator signal is used in the voltage converter and display timing generation circuit.
8.8 Display Timing Generator Circuit
This circuit generates some signals for displaying on LCD. The display clock, CL (internal), generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock and the display data latch circuit latches the 160-bit display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the MPU. The display clock generates an LCD AC signal (M) which enables the LCD driver to make an AC drive waveform. It also generates an internal common timing signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving waveform and internal timing signal are shown in Figure 8.8.1.
Figure 8.8.1 2-frame AC Driving Waveform (Duty Ratio: 1/160)
Ver 1.8
29/85
2006/9/18
ST7531
8.9 Liquid Crystal drive Circuit
This driver circuit is configured by 160-channel common drivers and 256-channel segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
COM0
COM1
COM8 COM9 COM10 COM11 COM12 COM13 COM14
COM2
SEG0
SEG 0 1 2 3 4
SEG1
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
8.10 Liquid Crystal Driver Power Circuit
The power supply circuit generates the voltage levels required to drive liquid crystal driver with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Table 8.10.1 shows the referenced combinations in using Power Supply circuits. Table 8.10.1 Recommended Power Supply Combinations User setup Only the internal power supply circuits are used Only the voltage regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used Power control (VB VR VF) 111 V/B circuits ON V/R circuits ON V/F circuits ON VLCD Open External input Open Open V0 Open V1 to V4 Open
011
OFF
ON
ON
Open External input External input
Open
001 000
OFF OFF
OFF OFF
ON OFF
Open External input
Ver 1.8
30/85
2006/9/18
ST7531
8.10.1 Voltage Converter Circuits
The Step-up Voltage Circuits
Note: The regulating capacitance on V0 ~ V4 should be between 1.0 to 2.2 F.
Ver 1.8
31/85
2006/9/18
ST7531
8.10.2 Voltage Regulator Circuits
SET VOP (SETVOP) The set VOP function is to program the optimum LCD supply voltage V0. SETVOP Reset state of VPR[8:0] is 257DEC = 13.88V. The V0 value is programmed via the VPR[8:0] register.
V0 = a + ( VPR[8:6]VPR[5:0]) x b Ex: VPR[5:0]=000001, VPR[8:6]=100 VPR[8:0]=100000001 3.6+257x0.04=13.88 where a is a fixed constant value 3.6, b is a fixed constant value 0.04, VPR[8:0] is the programmed V0 value with programming range from 5 to 410 (19AHEX), and VPR[5:0] is the set contrast value which can be set via the interface and is in two's complement format.(See command VOLUP & VOLDOWN)
The VPR[8:0] value must be in the V0 programming range as given in Fig.8.10.2. Evaluating equation (1), values outside the programming range indicated in Fig.8.10.2 may result.
V0
Programming range (05HEX to 19AHEX)
b
a
EC
00
01
02
03
04
05
06 ..... VPR[8:0] programming, (05hex to 19Ahex)
410
Fig. 8.10.2 V0 programming range Although the programming range for the internally generated V0 allows values above the maximum allowed V0, the customer has to ensure setting the VPR register and selecting the temperature compensation under all condition and including all tolerances that the maximum allowed V0 (20V) will never be exceeded.
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ST7531
Booster Efficiency By BOOSTER STAGES (2X, 3X, 4X, 5X, 6X, 7X, 8X) and BOOSTER EFFICIENCY (Level1~4) commands, we could easily set the best booster performance with suitable current consumption. If the booster efficiency is set to higher level (level4 is higher than level1), the boost efficiency is better than lower level, and it only needs a little bit more power consumption current. It could be applied to each multiple voltage condition. When the loading of LCD panel is heavier, the performance of booster will not be in a good working condition. The user may set the BE level to be higher and only a little bit more current needed. Never consider to change to higher booster stage at beginning stage unless it is necessary. The BOOSTER EFFICIENCY command could be used together with BOOSTER STAGE command to choose one best boost output condition. The user could regard the BOOSTER STAGE command as a large scale operation, and the BOOSTER EFFICIENCY command as a small scale operation. These commands are very convenient for using.
X6 Cap=1.0uF 18 16 14 12 VLCD 10 8 6 4 2 0 Open 90 K 80 K 70 K 60 K 50 K 40 K 30 K 20 K 10 K ohm ohm ohm ohm ohm ohm ohm ohm ohm Loading 3K 6K 12K 24K
Condition : VDD = 2.7V, Cap = 1.0uF, Booster = 6x, measured on chip
X7 Cap=1.0uF 20 18 16 14 12 10 8 6 4 2 0
oh m oh m oh m oh m oh m oh m oh m oh m O oh m pe n
3K 6K 12K 24K
VLCD
K
K
K
K
K
K
K
K 20
90
80
70
60
50
40
30
Loading
Condition : VDD = 2.7V, Cap = 1.0uF, Booster = 7x, measured on chip
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ST7531
RESET CIRCUIT When Power is Turned On Input power (VDD1~VDD5) Be sure to apply POWER-ON RESET (RST = LOW) Display control (DISCTRL) Setting clock dividing ratio: Duty setting: Setting reverse rotation number of line: Common scan direction (COMSCN) Setting scan direction: Temperature Gradient Setting (TMPGRD) Oscillation ON (OSCON) Sleep-out (SLIPOUT) Electronic volume control (VOLCTRL) Setting volume value: Setting built-in resistance value: Power control (PWRCTR) Setting operation of power supply circuit: <> All OFF 0 0 (3.95) <> Sleep-in Oscillation OFF COM0 -> COM79, COM80-> COM159 2 dividing 1/4 11H reverse rotations <>
Normal rotation of display (DISNOR)/Inversion of display (DISINV): Normal rotation of display Partial-in (PTLIN)/Partial-out (PTLOUT) Setting fix area: Area scroll set (ASSET) Setting area scroll region: Setting area scroll type: Scroll start set (SCSTART) Setting scroll start address: Data control (DATCTRL) Setting normal rotation/inversion of line address: Ver 1.8 34/85 Normal rotation 2006/9/18 <> 0 0 Full-screen scroll Partial-out 0
ST7531
Setting normal rotation/inversion of column address: Setting direction of address scanner: Setting RGB arrangement: Setting gradation: Line address set (LASET) Setting start line address: Setting end line address: Column address set (CASET) Setting start column address: Setting end column address: Memory write command (RAMWR) Writing displayed data: Repeat as many as the number needed and exit by entering other command. Wait until the power supply voltage has stabilized. Enter the command of power supply control first, and then wait at least 100ms before entering the display ON command when the built-in power supply circuit operates. If you do not wait, an unexpected display may appear on the liquid crystal panel. DISPLAY ON (DISON): DISPLAY OFF <> 0 0 0 0 <> Normal rotation Column direction RGB 65k-color
*1: When the IC is in SLEEP IN state, the liquid crystal drive power supply, the boosting power output, and GND pin are connected together, therefore, the SLEEP OUT command must be entered to cancel the SLEEP state prior to turning on the built-in circuit. (Note) If changes are unnecessary after resetting, command input is unnecessary.
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8. COMMANDS
8.1 Command table
Ext=0 or Ext=1
Index Command A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Function Hex Parameter 1 2 Ext In Ext Out 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 Ext=0 Set 30 Ext=1 Set 31 None None
Ext=0
Index Command A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DISON DISOFF DISNOR DISINV COMSCN DISCTRL SLPIN SLPOUT LASET CASET DATSDR RAMWR PTLIN PTLOUT ASCSET SCSTART OSCON OSCOFF PWRCTRL VOLCTRL VOLUP VOLDOWN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 0 1 0 1 0 1 1 1 1 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 Function Hex Parameter AF None AE None A6 None A7 None
1 Display On 0 Display Off 0 Normal Display 1 Inverse Display
1 COM Scan Direction BB 1 byte 0 Display Control 1 Sleep In 0 Sleep Out 1 Line Address Set CA 3 bytes 95 None 94 None 75 2 bytes
1 Column Address Set 15 2 bytes 0 Data Scan Direction 0 Writing to Memory 0 Partial display in 1 Partial display out 0 Area Scroll Set 1 Scroll Start Set 1 Internal OSC on 0 Internal OSC off 0 Power Control 1 EC control 0 EC increase 1 1 EC decrease 1 0 Not Use 0 READ Register1 1 READ Register2 1 NOP Instruction BC 3 bytes 5C Data A8 2 bytes A9 None AA 4 bytes AB 1 byte D1 None D2 None 20 1 byte 81 2 bytes D6 None D7 None 82 0 7C None 7D None 25 None
RESERVED 0 EPSRRD1 EPSRRD2 NOP 0 0 0
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27 28 STREAD EPINT 0 0 0 1 1 0 0 0 0 Read Data 0 0 1 1 Status Read 1 Initial code(1) 07 1 byte
Ext=1
Index Command A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 10 Gray 1 Set Gray 2 Set Wt. Set ANASET DITHOFF DITHON EPCTIN EPCOUT EPMWR EPMRD 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 Function Hex Parameter 16 bytes 16 bytes 3 bytes 3 bytes None None
FRAME 1 Gray PWM Set 20 FRAME 2 Gray PWM Set 21 Weight Set Analog Circuit Set Dithering Circuit Off Dithering Circuit On Control EEPROM Cancel EEPROM Write to EEPROM Read from EEPROM 22 32 34 35
CD 1 byte CC None FC None FD None
Note: The table above is for 8-bit interface. For the application of 16-bit interface, fill D15~8 with 0, and other bits are just the same with the table above.
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ST7531
EXT= "0" or "1"
(1) Extension instruction disable (EXT IN) - Parameter Byte: None (30H)
Use the "EXT=0" command table A0 Command 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0
(2) Extension instruction enable (EXT OUT) - Parameter Byte: None (31H)
Use the extended command table EXT="1" A0 Command 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1
EXT= "0"
(1) Display ON (DISON) - Parameter Byte: None (AFH) It is to turn the display on. When the display is turned on, segment and common outputs are generated at the level corresponding to the display data and display timing. As long as the sleep mode is selected, the display cannot be turned on. Thus, whenever using this command, the sleep mode must be cancelled first. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 1
(2) Display OFF (DISOFF) - Parameter Byte: None (AEH) It is to forcibly turn the display off. As long as the display is turned off, every segment and common outputs are forced to VSS level. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0
(3) Normal display (DISNOR) - Parameter Byte: None (A6H) It is to normally highlight the display area without modifying contents of the display data RAM. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0
(4) Inverse display (DISINV) - Parameter Byte: None (A7) It is to inversely highlight the display area without modifying contents of the display data RAM. This command does not invert non-display areas in case of using partial display. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 1
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(5) Common scan (COMSCN) - Parameter Byte: 1 (BBH) It is to specify the common output scan direction. This command is for the convenience of wiring on the LCD panel. A0 Command Parameter Byte 1 (PB1) 0 1 RD 1 1 WR 0 0 D7 1 * D6 0 * D5 1 * D4 1 * D3 1 * D2 0 D1 1 D0 1 Function Common Scan direction
CD2 CD1 CD0
When 1/160 is selected for the display duty, pins and common output are scanned in the order shown below. CD2 CD1 CD0 0 0 0 0 0 0 1 1 0 1 0 1 COM0 pin 0 0 79 79 Common scan direction COM79 pin COM80 pin 79 80 79 159 0 80 0 159 Original graphic : COM159 pin 159 80 159 80
Com0
Com80
Com79
Com159
CD[2-0] = [0,0,0] (0 79, 80 159) CD[2-0] = [0,0,1] (0 79, 159 80)
Com0
Com0
Com80
Com79
Com159
Com79
Com159
CD[2-0] = [0,1,0] (79 0, 80 159)
Com80
CD[2-0] = [0,1,1] (79 0, 159 80)
Com79
Com79
Com80
Com0
Com159
Com0
Com159
Com80
Figure 8.1.1 Common scan direction configuration
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(6) Display control (DISCTRL) - Parameter Byte: 3 (CAH) This command and succeeding parameters are used to perform the display timing-related setups. This command must be selected before using SLPOUT. Do not change this command while the display is turned on. A0 Command Parameter Byte 1 (PB1) Parameter Byte 2 (PB2) Parameter Byte 3 (PB3) 0 1 1 1 RD 1 1 1 1 WR 0 0 0 0 D7 1 * * * D6 1 * * * D5 0 * D4 0 0 D3 1 0 D2 0 CLD D1 1 0 D0 0 0 CL dividing ratio, F1 and F2 drive pattern. Function
DT5 DT4 DT3 DT2 DT1 DT0 Drive duty * FI LF3 LF2 LF1 LF0 FR inverse-set value
PB1 specifies the CL dividing ratio. CLD: CL dividing ratio. They are used to change number of dividing stages of external or internal clock. CLD=0: not divide, CLD=1: 2 divisions.
PB2 specifies the duty of the module on block basis. Initial: 00H (Numbers of display lines)/4-1 = DT5 x 2 + DT4 x 2 + DT3 x 2 + DT2 x 2 + DT1 x 2 + DT0 x 2 For example, 1/128 duty 128/4-1=31 (DT5, DT4, DT3, DT2, DT1, DT0) = (0, 1, 1, 1, 1, 1)
5 4 3 2 1 0
PB3 specifies number of line cycles (range from 2 to 16) in a frame. Number of line cycles-1 = LF3 x 2 + LF2 x 2 + LF1 x 2 + LF0 x 2 For example, 11 line cycles in a frame 11-1=10
3 2 1 0
(LF3, LF2, LF1, LF0) = (1, 0, 1, 0)
In the default, 11 line cycles in a frame is selected. FI decides the inversion type of frame at the end of common scan cycle while the number of duty is not divisible by the number of line cycles per frame. For example, in the application of 1/m duty and n line cycles in a frame set, the difference of the choice in FI is shown as the following figure. m = n x k + r, where m, n, k, and r are all whole numbers, and r is the remainder of m divided by n (r < n).
(7) Sleep in (SLPIN) - Parameter Byte: None (95H) This command is to enter the SLEEP MODE. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 0 D4 1 D3 0 D2 1 D1 0 D0 1
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(8) Sleep out (SLPOUT) - Parameter Byte: None (94H) This command is to exit the SLEEP MODE. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 0 D4 1 D3 0 D2 1 D1 0 D0 0
(9) Line address set (LASET) - Parameter Byte: 2 (75H) This command is to specify the line address area when MPU makes access to the display data RAM. As the addresses are increased from the start to the end line in the line-direction scan, the column address is increased by 1 and the line address return to the start line. Note that the start and end line must be a pair. Moreover, the relation "start line Note: The range of line address is 0 ~ 159.
(10) Column address set (CASET) - Parameter Byte: 2 (15H) This command is to specify the column address area when MPU makes access to the display data RAM. As the addresses are increased from the start to the end column in the column-direction scan, the line address is incremented by 1 and the column address is returned to the start column. Note that the start and end line must be a pair. Moreover, the relation "start column SC0 Start Column EC0 End Column
Note: The range of column address is 0 ~ 169. (11) Data scan direction (DATSDR) - Parameter Byte: 3 (BCH) This command is to setup various parameters in the operations of display data stored on the built-in RAM by MPU. A0 Command Parameter Byte 1 (PB1) Parameter Byte 2 (PB2) Parameter Byte 3 (PB3) 0 1 1 1 RD WR D7 1 1 1 1 0 0 0 0 1 * * * D6 0 * * * D5 1 * * * D4 1 * * * D3 1 * * * D2 1 0 * D1 0 CI * D0 0 LI Function Normal/inverse display of address and address scan direction.
CLR RGB arrangement
GS2 GS1 GS0 Gray-scale setup
PB1 is to specify the normal/inverse display of the line and column address and the address scanning direction. LI: Normal/inverse direction of the line address. LI =0: Normal, LI =1: Inverse CI: Normal/reverse direction of the column address. CI =0: Normal, CI =1: Reverse
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ST7531
(a) COMMAND #BCH, DATA #00H
(b) COMMAND #BCH, DATA #01H
(c) COMMAND #BCH, DATA #02H
(d) COMMAND #BCH, DATA #03H
Figure 8.1.2 Different RAM accessing setup under COMMAND #BBH, DATA #00H (a) COMMAND #BCH, DATA #00H (b) COMMAND #BCH, DATA #01H (c) COMMAND #BCH, DATA #02H (d) COMMAND #BCH, DATA #03H
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ST7531
PB2 is to change RGB arrangement of the segment output according to RGB arrangement on the LCD panel. This command will set the writing position of data (R, G, B) on the display memory to be changed or not.
CLR 0
Line 0, 3, 6, ... 1, 4, 7, ... 2, 5, 8, ... 0, 3, 6, ... 1, 4, 7, ... 2, 5, 8, ...
SEG0 R B G B G R
SEG1 G R B G R B
SEG2 B G R R B G
SEG3 R B G B G R
SEG4 G R B G R B
SEG5 B G R R B G
SEG6 R B G B G R
SEG7 G R B G R B
... ... ... ... ... ... ...
SEG254 B G R R B G
1
PB3 is to select desired display colors between the 32 gray-scale dithered 65K, 262K, or 16M. GS2 0 0 1 GS1 0 1 0 GS0 1 0 0 Numbers of gray-scale 32 gray-scale 65K 32 gray-scale 262K 32 gray-scale 16M
(12) Memory write (RAMWR) - Parameter Byte: Numbers of data written (5CH) This command turns on the data entry mode when MPU writes data to the display memory. This command will always sets the line and column address at the start address while executed. The following parameter byte rewrites contents of the display data RAM and increases the line or column address automatically. The write mode is automatically cancelled if any other command is entered. 1. 8-bit bus Command Parameter Byte 1 (PB1) 2. 16-bit bus A0 RD RW D15 D14 ... Command 010 * * ... Parameter Byte 1 (PB1) 1 1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 * * 0 1 0 1 1 1 0 0 Data to be written Function Memory write Write date A0 0 1 RD RW 1 0 1 0 D7 0 D6 1 D5 0 D4 D3 D2 1 1 1 Data to be written D1 0 D0 0 Function Data to be written
(13) Partial in (PTLIN) - Parameter Byte: 2 (A8H) This command is to specify the partial display area. It will turn on partial display of the screen (dividing screen by lines) to save power. Since ST7531 processes the liquid crystal display signal on 4-line basis (block basis), the display and no-display areas are also specified on 4-bit line (block basis). Command Parameter Byte 1 (PB1) Parameter Byte 2 (PB2) A0 0 1 1 RD 1 1 1 RW 0 0 0 D7 1 * * D6 0 * * D5 D4 D3 D2 D1 D0 Function 1 0 1 0 0 0 -PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 Start block address PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 End block address
Only the address of the display block can be specified for the partial display. Do not specify an address not to be displayed when scrolled.
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(14) Partial out (PTLOUT) - Parameter Byte: none (A9H) This command is to exit the PARTIAL DISPLAY MODE. Command A0 0 RD 1 RW 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 1
(15) Area scroll set (ASCSET) - Parameter Byte: 4 (AAH) It is to scroll only the specified portion of the screen (dividing the screen by lines). This command specifies the scrolling type of area, fixed area and scrolled area. A0 RD RW D7 D6 Command Parameter Byte 1 (PB1) Parameter Byte 2 (PB2) Parameter Byte 3 (PB3) Parameter Byte 4 (PB4) 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 * * * * 0 * * * * D5 1 TB5 BB5 D4 0 TB4 BB4 D3 1 TB3 BB3 D2 0 TB2 BB2 D1 1 TB1 BB1 D0 0 -Function
TB0 Top block address BB0 Bottom block address
NSB5 NSB4 NSB3 NSB2 NSB1 NSB0 Number of specified blocks * * * * SCM1 SCM0 Area scroll mode
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PB4: It is used to specify the scrolling mode. Settings SCM1 SCM0 Scrolling Mode Top block address (TB) Bottom block address (BB) (NSB) 0 0 1 1 0 1 0 1 Center mode Top mode Bottom mode Whole mode Top(fixed area) height = Top address 0 Top(fixed area) height = Top address 0 Bottom(fixed area) height = 39-Bottom address Bottom(fixed area) height = 39-Bottom address 39 39 Bottom start address = Specified number Bottom start address = Specified number 39 39 Number of specified blocks
Since ST7531 processes the liquid crystal display signals on the four-line basis (block basis), fixed and scrolled areas are also specified on the four-line basis (block basis). DDRAM address of the top fixed area is set in the block address increasing direction starting with the 0 block. DDRAM address of the bottom fixed area is set in the block address decreasing direction starting with 39
st th
block. The DDRAM address of other blocks fixed areas are assigned to the scrolled + background areas.
PB1 is to specify the top block address of the scrolled + background areas. Specify the 0 block for the top screen scroll or whole screen scroll. PB2 specifies the bottom address of the scroll + background areas. Specify the 39 block for the bottom or whole screen scroll. The relation that top block address < bottom block address must be maintained. PB3 specifies a specific number of blocks {Numbers of (Top fixed area +Scroll area) block-1}. In the case of the bottom scroll or whole screen scroll, the value is identical with PB2.
th th
The user can turn on the area scroll function by executing the area scroll set command first and then specifying the display start block of the scroll area with the scroll start set command.
(16) Scroll start address set (SCSTART) - Parameter Byte: 1 (ABH) This command is to specify which line address of DDRAM to be the start line content shown on screen. Note that you must execute this command after executing the area scroll set command. Scroll becomes available by dynamically changing the start block address. Command Parameter Byte 1 (PB1) A0 0 1 RD 1 1 RW 0 0 D7 1 * D6 0 * D5 1 SB5 D4 0 SB4 D3 1 SB3 D2 0 SB2 D1 1 SB1 D0 Function 1 -SB0 Start block address
Note : Don't repeat "Area scroll set(AAH)" instruction when "Scroll start address set" is executed.
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(17) Internal oscillation on (OSCON) - Parameter Byte: none (D1H) This command turns on the internal oscillation circuit. It is valid only when the internal oscillation circuit CLS = HIGH. Command A0 0 RD 1 RW 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1
(18) Internal oscillation off (OSCOFF) - Parameter Byte: none (D2H) It turns off the internal oscillation circuit. The circuit is also turned off in the reset mode. Command A0 0 RD 1 RW 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0
(19) Power control set (PWRCTRL) - Parameter Byte: 1 (20H) This command is used to turn on or off the Booster circuit, voltage regulator circuit, and reference voltage. Command Parameter Byte 1 (PB1) A0 0 1 RD 1 1 RW 1 0 D7 0 * D6 0 * D5 1 * D4 0 0 D3 0 VB D2 0 0 D1 0 VF D0 0 VR Function -LCD drive power
VR turns on/off the reference voltage generation circuit. VR = "1": ON, VR =" 0": OFF VF turns on/off the circuit voltage follower. VF = "1": ON, VF =" 0": OFF VB: It turns on or off the Booster. VB = "1": ON, VB =" 0": OFF
(20) Electronic volume control (VOLCTRL) - Parameter Byte: 2 (81H)
The command is used to program the optimum LCD supply voltage V0. Refer to 8.10.2.
Command Parameter Byte 1 (PB1) Parameter Byte 2 (PB2) A0 0 1 1 RD 1 1 1 RW 0 0 0 D7 1 * * D6 0 * * D5 D4 D3 D2 D1 D0 Function 0 0 0 0 0 1 -VPR5 VPR4 VPR3 VPR2 VPR1 VPR0 VPR[5:0] * * * VPR8 VPR7 VPR6 VPR[8:6]
With the VOLUP and VOLDOWN command the V0 voltage and therewith the contrast of the LCD can be adjusted.
(21) Increment electronic control (VOLUP) - Parameter Byte: none (D6H) This command increments electronic control offset value of voltage regulator (V0) circuit by 1. Each step is 0.04V. Command A0 0 RD 1 RW 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 1 D1 1 D0 0
If you set the electronic control value to 111111, the control value is set to 000000 after this command has been executed.
(22) Decrement electronic control (VOLDOWN) - Parameter Byte: none (D7H) This command decrements electronic control offset value of voltage regulator (V0) circuit by 1. Each step is 0.04V. Command A0 0 RD 1 RW 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 1 D1 1 D0 1
If you set the electronic control value to 000000, the control value is set to 111111 after this command has been executed.
(23) Reserved (82H) Do not use this command. Command A0 0 RD 1 RW 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0
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(24) Read Register 1 (EPSRRD1) Command: 1 Parameter Byte: none (7CH) Execute the EPSRRD1 and STREAD (Status Read) commands in succession to read the Electronic Control value. Command A0 0 RD 1 RW 0 D7 0 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 0
Execute the Status Read command immediately after this command and execute the NOP command after the STREAD (Status Read) command.
(25) Read Register 2 (EPSRRD2) Command: 1 Parameter Byte: none (7DH) Execute the EPSRRD2 and STREAD (Status Read) commands in succession to read the built-in resistance ratio. Command A0 0 RD 1 RW 0 D7 0 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 1
Execute the Status Read command immediately after this command and execute the NOP(Reset) command after the STREAD (Status Read) command.
(26) Non-operating (NOP) - Parameter Byte: none (25H) This command does not affect the operation but has the function of canceling the IC test mode. Thus, it is recommended to enter it periodically to prevent malfunctioning due to noise and so on. Command A0 0 RD 1 RW 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 1
(27) Status read (STREAD) - Parameter Byte: none The command is to read the internal condition of the IC. One status can be displayed depending on the setting status after reset or after NOP operation. Command A0 0 RD 0 RW D7 D6 1 Status data D5 D4 D3 D2 D1 D0
D7: Area scroll mode D6: Area scroll mode D5: RMW on/off D4: Scan direction D3: Display ON/OFF D2: EEPROM access D1: Display normal/inverse D0: Partial display
Refer to SCM1 (ASCSET) Refer to SCM0 (ASCSET) 0 : Out 0 : Column 0 : OFF 0: OutAccess 0 : Inverse 0 : OFF 1 : In 1 : Line 1 : ON 1: InAccess 1 : Normal 1 : ON
(28) Initial code (1) (EPINT) Command: 1; Parameter: 1 (07H) A0 Command Parameter(P1) 0 1 RD 1 1 RW 0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 1 D3 0 1 D2 1 0 D1 1 0 D0 1 1 07H 19H Function
This command is used for EEPROM internal ACK signal generating ,suggest using this command before EEPROM read/write operation . This command improve the EEPROM internal ACK signal under unstable power system.
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EXT="1"
The ST7531 applies 16-gray level and 2 FRC to achieve 32-gray scale display. Every gray level is in the strength controlled by 31-PWM (5-bit). The following 2 commands are to set the gray scale value. (1) Set Gray 1 value (Gray 1 set) - Parameter Byte: 16 (20H)
Command Gray1 Set Parameter Byte 1 (PB1) Parameter Byte 2 (PB2) A0 RD WR D7 D6 D5 0 1 1 1 1 1 0 0 0 0 * * 0 * * 1 * * D4 0 G0F14 G1F14 D3 0 G0F13 G1F13 D2 0 G0F12 G1F12 D1 0 G0F11 G1F11 D0 0 Function ODD FRAME Gray PWM Set
G0F10 Set Gray level 0 at odd frames G1F10 Set Gray level 1 at odd frames
Parameter Byte 14 (PB14)
1
1
0
*
*
*
G13F14 G13F13 G13F12 G13F11 G13F10 Set Gray level 13 at odd frames
Parameter Byte 16 (PB16)
1
1
0
*
*
*
G15F14 G15F13 G15F12 G15F11 G15F10 Set Gray level 15 at odd frames
(2)
Set Gray 2 value (Gray 2 set) - Parameter Byte: 16 (21H)
Command Gray1 Set A0 RD WR D7 D6 D5 0 1 1 1 1 1 0 0 0 0 * * 0 * * 1 * * D4 0 G0F24 G1F24 D3 0 G0F23 G1F23 D2 0 G0F22 G1F22 D1 0 G0F21 G1F21 D0 1 Function EVEN FRAME Gray PWM Set
Parameter Byte 1 (PB1) Parameter Byte 2 (PB2)
G0F20 Set Gray level 0 at even frames G1F20 Set Gray level 1 at even frames
Parameter Byte 14 (PB14)
1
1
0
*
*
* G13F24 G13F23 G13F22 G13F21 G13F20 Set Gray level 13 at even frames
Parameter Byte 16 (PB16)
1
1
0
*
*
* G15F24 G15F23 G15F22 G15F21 G15F20 Set Gray level 15 at even frames
(3)
Weight Set (Wt. set) - Parameter Byte: 3 (22H) A0 0 1 1 1 RD RW 1 0 1 0 1 0 1 0 D7 0 * * * D6 0 * * * D5 D4 D3 D2 D1 D0 Function 1 0 0 0 1 0 --* * * WT2 WT1 WT0 * ED4 ED3 ED2 ED1 ED0 set edge detector detect value * * * * EE WE
Command Parameter Byte 1 (PB1) Parameter Byte 2 (PB2) Parameter Byte 3 (PB3)
PB1: Weighting Set Compared with stripe, SPRD uses fewer channels but lost only a little part of display information. The additional "Weighting set" is to recompense color information. In normal display, there is relativity of color between pixel and pixel. Therefore, the lost element can be used to compensate the next pixel and enhance the display quality. The sum of all "Weight set" values should be equal to "1" :
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R(x-1,y-1) + R(x,y-1) + R(x+1,y-1) + R(x-1,y) + R(x,y) + R(x+1,y) + R(x-1,y+1) + R(x,y+1) + R(x+1,y+1) = 1 G(x-1,y-1) + G(x,y-1) + G(x+1,y-1) + G(x-1,y) + G(x,y) + G(x+1,y) + G(x-1,y+1) + G(x,y+1) + G(x+1,y+1) = 1 B(x-1,y-1) + B(x,y-1) + B(x+1,y-1) + B(x-1,y) + B(x,y) + B(x+1,y) + B(x-1,y+1) + B(x,y+1) + B(x+1,y+1) = 1
WT2 0 0 0 0 1
WT1 0 0 1 1 0
WT0 0 1 0 1 0
Weighting k 0/8 1/8 2/8 3/8 (default) 4/8
Assume the dots on display are arranged as follows.
D0 D1 ... Di ... Dn-1 Dn
After processed, Di will become kDi-1+(1-k) Di. In addition, the new value will be saved as Di`- the new Di in RAM.
PB2: set edge detector detect value
ED4 ED3 ED2 ED1 ED0 detect value 0 0 0 0 00 0 0 0 0 11 0 0 0 1 02 0 0 0 1 13 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 0 0 1 1 0 1 0 1 0 0 1 0 1 When "Edge detect" is enabled, the difference value between pixel and pixel which is large enough will activate the "Weight set" function.
14 15 16 17 18 28 29 30 31
(default)
PB3: EE 0 0 1 *: don't care WE 0 1 * no weighting weighting enable weighting + edge detect
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(4) Analog circuit set (ANASET) - Parameter Byte: 3 (32H) A0 Command Parameter Byte 1 (PB1) Parameter Byte 2 (PB2) Parameter Byte 3 (PB3) 0 1 1 1 RD 1 1 1 1 WR 0 0 0 0 D7 0 * * * D6 0 * * * D5 1 * * * D4 1 * * * D3 0 * * * D2 0 * BS2 D1 1 BE1 BS1 D0 0 Function
OSF2 OSF1 OSF0 OSC frequency Adjustment BE0 Booster Efficiency Set BS0 Bias setting
PB1: Oscillator frequency adjustment OSF2 0 1 0 1 0 1 0 1 OSF1 0 0 1 1 0 0 1 1 OSF0 0 0 0 0 1 1 1 1 Frequency (KHz) 12.7 (Default) 13.2 14.3 15.7 17.3 19.3 21.9 25.4
Condition : 1/160 duty, fCL(Hz) = Frame frequency x (duty + 1dummy )
PB2: Booster Efficiency set BE1 0 0 1 1 BE0 Frequency on booster capacitors (Hz) 0 1 0 1 3K 6K (Default) 12K 24K
PB3: Select LCD bias ratio of the voltage required for driving the LCD. BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 LCD bias 1/14 1/13 1/12 1/11 1/10 1/9 1/7 1/5
(5)
Color Dither OFF (DITHOFF) - Parameter Byte: None (34H)
Turn off the dithering circuit. Command A0 0 RD 1 RW 0 D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0
(6)
Color Dither ON (DITHON) - Parameter Byte: None (35H)
Turn on the dithering circuit. Command A0 0 RD 1 RW 0 D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 1
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(7) Control EEPROM (EPCTIN) - Parameter Byte: 1 (CDH) A0 0 1 RD 1 1 RW 0 0 D7 1 0 D6 1 0 D5 0 EEWR D4 0 0 D3 1 0 D2 1 0 D1 0 0 D0 1 0
Command Parameter Byte 1 (PB1)
When EEWR = "1", EEPROM will be Write Enable; when EEWR = "0", EEPROM will be Read Enable.
(8)
Cancel EEPROM Command (EPCOUT) - Parameter Byte: None (CCH)
This command is to cancel the EEPROM Read/Write Enable. Command A0 0 RD 1 RW 0 D7 1 D6 1 D5 0 D4 0 D3 1 D2 1 D1 0 D0 0
(9)
Write data to EEPROM (EPMWR) - Parameter Byte: None (FCH)
This command is to Write data to EEPROM. Command A0 0 RD 1 RW 0 D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 0
(10) Read data from EEPROM (EPMRD) - Parameter Byte: None (FDH) This command is to Read data from EEPROM. Command A0 0 RD 1 RW 0 D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 1
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8.2 Referential Instruction Setup Flow
8.2.1 EEPROM Setting Flow
The ST7531 provide the Write and Read function to write the Electronic Control value into and read them from the built-in EEPROM. Using the Write and Read functions, you can store these values appropriate to each LCD panel. This function is very convenient for user in setting from some different panel's voltage. But using this function must attention the setting procedure. Please see the following diagram. Note: When "Writing" value to EEPROM, the voltage of VOUTIN must be more than 18V.
EC Value Adjustment Flow
Make sure the Action: End of Initialization Flow Initial Code(1) OSC On Power Control On Increase or decrease EC value ( command D6H or D7H ) ( get the V0 value you need )
Wait for 100ms
Write into EEPROM (command FCH)
Wait for 100ms Close Extension mode (command 30H) Disable EEPROM (command CCH) Display Off (command AEH)
Close Extension mode (command 30H)
Initial Code(1) (command 07H) (parameter 19H)
Display On (command AFH)
Open Extension mode (command 31H)
Turn off the power
Enable EEPROM (command CDH) (parameter 20H)
Wait for 100ms
Turn on the power
Check the EC value
Figure 8.2.1.1 Flow of EC value adjustment and writing into EEPROM
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Note: When "Reading" value from EEPROM, the voltage of VOUTIN must be more than 6V.
Ext=0 (command 30H)
Initial code(1) (command 07H) (parameter 19H) Ext=1 (command 31H)
control EEPROM (command CDH) (parameter 00H)
Wait for 100ms
Write to EEPROM (command FDH)
Wait for 100ms
cancel EEPROM (command CCH) Ext=0 (command 30H)
Figure 8.2.1.2 EEPROM Reading flow
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ExampleEEPROM Read Operation
void ReadEEPROM( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x0007 ); Write( DATA, 0x0019 ); Write( COMMAND, 0x0031 ); Write( COMMAND, 0x00CD ); Write( DATA, 0x0000 ); Delay( 100ms ); Write( COMMAND, 0x00FD ); Delay( 100ms ); Write( COMMAND, 0x00CC ); Write( COMMAND, 0x0030 ); } // Ext = 0 // Initial code (1) // Ext = 1 // EEPROM ON // Entry "Read Mode" // Waite for EEPROM Operation ( 100ms ) // Start EEPROM Reading Operation // Waite for EEPROM Operation ( 100ms ) // Exist EEPROM Mode // Ext = 0
ExampleEEPROM Write Operation
void WriteEEPROM( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AE ); Write( COMMAND, 0x0007 ); Write( DATA, 0x0019 ); Write( COMMAND, 0x0031 ); Write( COMMAND, 0x00CD ); Write( DATA, 0x0020 ); Delay( 100ms ); Write( COMMAND, 0x00FC ); Delay( 100ms ); Write( COMMAND, 0x00CC ); Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AF ); } // Ext = 0 // Display OFF // Initial code(1) // Ext = 1 // EEPROM ON // Entry "Write Mode" // Waite for EEPROM Operation ( 100ms ) // Start EEPROM Writing Operation // Waite for EEPROM Operation ( 100ms ) // Exist EEPROM Mode // Ext = 0 // Display ON
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8.2.2 Initializing with the Built-in Power Supply Circuits
Figure 8.2.2.1 Initializing with the Built-in Power Supply Circuits When Power-ON (VDD/VDD2 goes from low to high), please follow the sequence shown below. If not, some unpredictable result may occur.
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ExampleInitial code for 170X160
void ST7531_Init( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x0094 ); Write( COMMAND, 0x00D1 ); Write( COMMAND, 0x0020 ); Write( DATA, 0x0008 ); Delay( 1ms ); Write( COMMAND, 0x0020 ); Write( DATA, 0x000B ); Write( COMMAND, 0x0081 ); Write( DATA, 0x0004 ); Write( DATA, 0x0004 ); Write( COMMAND, 0x00CA ); Write( DATA, 0x0000 ); Write( DATA, 0x0027 ); Write( DATA, 0x0000 ); Write( COMMAND, 0x00A6 ); Write( COMMAND, 0x00BB ); Write( DATA, 0x0001 ); Write( COMMAND, 0x00BC ); Write( DATA, 0x0000 ); Write( DATA, 0x0000 ); Write( DATA, 0x0001 ); Write( COMMAND, 0x0075 ); Write( DATA, 0x0000 ); Write( DATA, 0x009F ); Write( COMMAND, 0x0015 ); Write( DATA, 0x0000 ); Write( DATA, 0x00A9 ); Write( COMMAND, 0x0031 ); Write( COMMAND, 0x0032 ); Write( DATA, 0x0000 ); Write( DATA, 0x0001 ); Write( DATA, 0x0000 ); Write( COMMAND, 0x0034 ); ReadEEPROM(); Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AF ); } //Ext = 0 //Sleep Out //OSC On //Power Control Set //Booster Must Be On First //Power Control Set //Booster, Regulator, Follower ON //Electronic Control //Vop=14.0V
//Display Control //CL=X1 //Duty=160 //FR Inverse-Set Value // Normal Display //COM Scan Direction // 079 15980 //Data Scan Direction //Normal //RGB Arrangement //65K COLOR //Line Address Set //Start Line=0 //End Line =159 //Column Address Set //Start Column=0 //End Column =169 //Ext = 1 //Analog Circuit Set //OSC Frequency =000 (Default) //Booster Efficiency=01(Default) //Bias=1/14 //Dithering Off //Read EEPROM Flow //Ext = 0 //Display On
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8.2.3 Data Displaying
Normal State
Display Data RAM Addressing by Instruction [Data Control: BCH] [Set Line Address: 75H] [Set Column Address: 15H] [Entry Memory Write Mode: 5CH]
Display Data Write [Display Data Write]
No
End of Display Data Write ?
Yes
End of Data Display
Figure 8.2.3.1 Data Displaying
ExampleDisplay for 170X160
void Display( char *pattern ) { unsigned char i, j; Write( COMMAND, 0x0030 ); Write( COMMAND, 0x0015 ); Write( DATA, 0x0000 ); Write( DATA, 0x00A9 ); Write( COMMAND, 0x0075 ); Write( DATA, 0x0000 ); Write( DATA, 0x009F); Write( COMMAND, 0x005C ) for( j = 0; j < 160 ; j++ ) For( i = 0 ; i < 170 ; i++ ) Write( DATA, pattern[ j * 160 + i ] ); // Ext = 0 // Column address set // From column0 to column169 // Page address set // From line0 to line159 // Entry Memory Write Mode
// Display Data Write
}
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8.2.4 Partial Display In/Out
Figure 8.2.4.1 Partial Display In/Out
ExamplePartial Display In/Out Operation
void PartailIn( unsigned char start_block, unsigned char end_block ) { Write( COMMAND, 0x0030 ); // Ext = 0 Write( COMMAND, 0x00A8); // Partial Display In Function Write( DATA, start_block ); // Start Block Write( DATA, end_block ); // End Block } void PartailOut( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00A9 ); }
// Ext = 0 // Partial Display Out Function
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extern unsigned char *display_pattern; void main() { PartialIn( 11, 18 ); Windowing( 0, 11*4, 169, 18*4 ); PartialDisplay( display_pattern ); . . . PartialOut(); } // entry partial display mode // set the page and column range // Fill the data into partial display area
// Out of partial display mode
8.2.5 Scroll Display
Figure 8.2.5.1 Scroll Display
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ExampleScreen Scroll Operation
void CenterScreenScroll( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AA); Write( DATA, 0x000A ); Write( DATA, 0x0014 ); Write( DATA, 0x0014 ); Write( DATA, 0x0000 ); ScrollUp() or ScrollDown(); } void TopScreenScroll( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AA); Write( DATA, 0x0000 ); Write( DATA, 0x0014 ); Write( DATA, 0x0014 ); Write( DATA, 0x0001 ); ScrollUp() or ScrollDown(); } void BottomScreenScroll( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AA); Write( DATA, 0x000A ); Write( DATA, 0x0019 ); Write( DATA, 0x0019 ); Write( DATA, 0x0002 ); ScrollUp() or ScrollDown(); } void WholeScreenScroll( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AA); Write( DATA, 0x0000 ); Write( DATA, 0x0019 ); Write( DATA, 0x0019 ); Write( DATA, 0x0003 ); ScrollUp() or ScrollDown(); } // Ext = 0 // Partial Display In Function // Top_Block=0 // Bottom_Block=25 // Number of Specified Blocks=Bottom_Block=25 // Area Scroll Type=Whole Screen Scroll // Scroll Up or Scroll Down // Ext = 0 // Partial Display In Function // Top_Block=10 // Bottom_Block=25 // Number of Specified Blocks=Bottom_Block=25 // Area Scroll Type=Bottom Screen Scroll // Scroll Up or Scroll Down // Ext = 0 // Partial Display In Function // Top_Block=0 // Bottom_Block=20 // Number of Specified Blocks=Bottom_Block=20 // Area Scroll Type=Top Screen Scroll // Scroll Up or Scroll Down // Ext = 0 // Partial Display In Function // Top_Block=10 // Bottom_Block=20 // Number of Specified Blocks=Bottom_Block=20 // Area Scroll Type=Center Screen Scroll // Scroll Up or Scroll Down
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void ScrollUp( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AB); Write( DATA, Top_Block); Delay(); Write( COMMAND, 0x00AB); Write( DATA, Top_Block +1 ); Delay(); Write( COMMAND, 0x00AB); Write( DATA, Top_Block +2 ); Delay(); ...... ...... Write( COMMAND, 0x00AB); Write( DATA, Bottom_Block ); Delay(); } void ScrollDown( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AB); Write( DATA, Bottom_Block); Delay(); Write( COMMAND, 0x00AB); Write( DATA, Bottom_Block -1 ); Delay(); Write( COMMAND, 0x00AB); Write( DATA, Bottom_Block -2 ); Delay(); ...... ...... Write( COMMAND, 0x00AB); Write( DATA, Top _Block ); Delay(); } // Ext = 0 // Scroll Start Set // Start Block Address= Bottom_Block // Delay // Scroll Start Set // Start Block Address= Bottom_Block -1 // Delay // Scroll Start Set // Start Block Address= Bottom_Block -2 // Delay // Ext = 0 // Scroll Start Set // Start Block Address=Top_Block // Delay // Scroll Start Set // Start Block Address= Top_Block+1 // Delay // Scroll Start Set // Start Block Address= Top_Block +2 // Delay
// Scroll Start Set // Start Block Address= Bottom_Block // Delay
// Scroll Start Set // Start Block Address= Top_Block // Delay
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8.2.6 Display On / OFF
Normal State
Display OFF State
[Set Display OFF : AEH] End of Display OFF
Figure 8.2.6.1 Display Off
[Set Display ON : AFH]
End of Display ON
Figure 8.2.6.2 Display On
ExampleDisplay OFF Operation
void DisplayOff( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AE ); } // Ext = 0 // Display Off
ExampleDisplay ON Operation
void DisplayOn( void ) { Write( COMMAND, 0x0030 ); Write( COMMAND, 0x00AF ); } // Ext = 0 // Display On
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8.2.7 Power OFF
Normal State
Execute the "Sleep In Flow"
Keeping /RES Pin ="L"
Power Off (VDD-VSS)
End of Power OFF
VDD
/RES
tR Internal State Normal State Execute "Sleep In Flow" Reset
tR > 12 ms
Power Off
After Sleep In Flow, keep the /RES = Low
Figure 8.2.7.1 Power off
NoteThe sequence is that users must set the VDD to low after keeping the /RES=low time longer than 12ms.
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9. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2. Parameter Power Supply Voltage Power supply voltage VDD5 Power supply voltage (VDD standard) Power supply voltage (VDD standard) Input voltage Output voltage Operating temperature(Die) Storage temperature(Die) VLCDIN, VLCDOUT V0,V1, V2, V3, V4 VIN VO TOPR TSTR -0.5 ~ +20 0.3 to VLCDIN -0.5 to VDD+0.5 -0.5 to VDD+0.5 -30 to +85 -40 to +125 V V V V C C Symbol VDD, VDD1 VDD2, VDD3, VDD4, -0.5 ~ +4.0 V Conditions -0.5 ~ +4.0 V Unit
VLCD
V0 to V4
VDD
VDD
VSS System (MPU) side
VSS ST7530 chip side
VSS
Notes 1. Stresses above those listed under Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 3. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VLCDIN V0 V1 V2 V3 V4 Vss
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10. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices").
11. DC CHARACTERISTICS
Ta = -30 to +85 Rating Item Symbol Condition Min. Operating Voltage (1) VDD VDD1 VDD2 VDD3 VDD4 VDD5 VIH VIL IOH IOL ILI 2.4 Typ. Max. 3.3 V Units Pin VDD*1 VDD1 VDD2 VDD3 VDD4 VDD5 *2 *2 *3 *3 *4 Applicable
Operating Voltage (2) High-level Input Voltage Low-level Input Voltage High-level Output Current Low-level Output Current Input leakage current
(Relative to VSS) VDD=2.7V VOH =2.2V VDD=2.7V VOL = 0.5V VIN = VDD or VSS Ta = 25C
2.4 0.7 VDD VSS 0.5 -1.0
-
3.3 VDD 0.3 VDD -0.5 1.0
V V V mA mA A
Liquid Crystal Driver ON RON Resistance
(Relative To VSS) V0 = 14.0V VDD = 2.7V 1.4 2.0 K
SEGn COMn *5
Internal Oscillator Oscillator Frequency External Input
fOSC 1/160 duty fCL Ta = 25C VDD = 2.7V
-
12.4 12.4 78
26 26 160
kHz kHz Hz
CL*6 CL SEGn
Frame frequency fFRAME
CLD = 0
Rating Item Input voltage Internal Power Supply Step-up output VLCDOUT voltage Circuit Voltage regulator Circuit Operating Voltage * Recommended LCD VOP voltage is 12V~14V . VLCDIN (Relative To VSS) 18 V VLCDIN (Relative To VSS) 18 V VLCDOUT Symbol VDD Condition Min. (Relative To VSS) 1.8 Typ. Max. 3.3 V VDD Units Applicable Pin
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Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used . Rating Test pattern Symbol Condition Min. VDD = 2.8 V, V0 - VSS = 16.0 V Booster = 6x Bias = 1/12 Duty = 1/160 Bare chip Cap = 1.0uF Ta = 25C Typ. Max. Units Notes (Used die to measure)
Display Pattern ISS (checkerboard)
-
460
600
A
*7
Power Down
ISS
-
-
10
A
-
Notes to the DC characteristics 1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load, and Internal clock 2. Power-down mode. During power down all static currents are switched off. 3. If external VLCD, the display load current is not transmitted to IDD. 4. VLCD external voltage applied to VLCDIN pin; VLCDIN disconnected from VLCDOUT
References for items marked with *
*1. While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2. The A0, D0 to D5, D6 (SI), D7 (SCL),D8 to D15 /RD(E), /WR(R/W), XCS,CL , RST . *3. The D0 to D7, D8 to D15 and CL. *4. The A0,/RD (E), /WR(R/W), XCS, CLS, CL, RST , IF1 to IF3, M0, M1. *5. These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage range. RON = 0.1 V /I (Where I is the current that flows when 0.1 V is applied while the power supply is ON.) *6. The relationship between the oscillator frequency and the frame rate frequency. *7. It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.
ST7531 I/O PIN ITO Resister Limitation
PIN Name IF1~IF3, M0, M1, CLS VREF, T0~T10, TCAP, CL VDD,VDD1~5,VSS,VSS1,VSS2,VSS4, VLCDIN, VLCDOUT , CxP, CxN V0IN, V0OUT, V1, V2, V3, V4 A0, RW_WR, E_RD, XCS, D0 ...D15, SCL, SI RST ITO Resister No Limitation Floating <100 <500 <1k <10k
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12. AC CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8
tAH8
XCS tCYC8 tCCLR,tCCLW WR,RD tCCHR,tCCHW tDS8 D0 to D7 (Write) tDH8
tACC8 D0 to D7 (Read)
tOH8
Figure 39.
(VDD = 3.3V , Ta = -30 to 85C,Die) Rating Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) WR Enable H pulse width (WRITE) Enable L pulse width (READ) RD Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time D0 to D7 READ access time READ Output disable time tACC8 tOH8 CL = 100 pF CL = 100 pF 40 30 tCCHR tDS8 tDH8 100 150 20 tCCHW tCCLR 100 100 ns A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW Condition Min. 20 20 200 100 Max. Units
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(VDD = 2.7V , Ta = -30 to 85C,Die) Rating Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) WR Enable H pulse width (WRITE) Enable L pulse width (READ) RD Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time D0 to D7 READ access time READ Output disable time tACC8 tOH8 CL = 100 pF CL = 100 pF 40 30 tCCHR tDS8 tDH8 100 200 20 tCCHW tCCLR 100 150 ns A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW Condition Min. 20 30 250 150 Max. Units
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between XCS being "L" and WR and RD being at the "L" level.
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System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
A0 R/W tAW6 tAH6
XCS tCYC6 tCCLR,tCCLW E tCCHR,tCCHW tDS6 D0 to D7 (Write) tDH6
tACC6 D0 to D7 (Read)
tOH6
Figure 40.
(VDD = 3.3V , Ta = -30 to 85C,Die) Rating Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) WR Enable H pulse width (WRITE) Enable L pulse width (READ) RD Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time D0 to D7 READ access time READ Output disable time tACC6 tOH6 CL = 100 pF CL = 100 pF 40 30 tEWHR tDS6 tDH6 100 150 20 tEWHW tEWLR 100 100 ns A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW Condition Min. 20 20 200 100 Max. Units
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(VDD = 2.7V , Ta = -30 to 85C,Die) Rating Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) WR Enable H pulse width (WRITE) Enable L pulse width (READ) RD Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time D0 to D7 READ access time READ Output disable time tACC6 tOH6 CL = 100 pF CL = 100 pF 40 30 tEWHR tDS6 tDH6 100 200 20 tEWHW tEWLR 100 150 ns A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW Condition Min. 20 30 250 150 Max. Units
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between XCS being "L" and E.
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SERIAL INTERFACE (4-Line Interface)
tCCSS tCSH
XCS
tSAS A0 tSCYC tSLW SCL
tSAH
tSHW tf tSDS SI tr tSDH
Fig 41. (VDD = 3.3V , Ta = -30 to 85C,Die) Rating Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time A0 Address hold time Data setup time SI Data hold time CS-SCL time XCS CS-SCL time tCSH 50 (VDD = 2.7V , Ta = -30 to 85C,Die) Rating Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time A0 Address hold time Data setup time SI Data hold time CS-SCL time XCS CS-SCL time tCSH 60 tSDH tCSS 40 30 tSAH tSDS 40 40 ns SCL Signal Symbol tSCYC tSHW tSLW tSAS Condition Min. 11 0 60 50 50 Max. Units tSDH tCSS 30 20 tSAH tSDS 30 30 ns SCL Signal Symbol tSCYC tSHW tSLW tSAS Condition Min. 100 50 50 40 Max. Units
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*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
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SERIAL INTERFACE (3-Line Interface)
tCCSS tCSH
XCS
tSCYC tSLW SCL tSHW tf tSDS SI tr tSDH
Fig 42. (VDD = 3.3V , Ta = -30 to 85C,Die) Rating Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time SI Data hold time CS-SCL time XCS CS-SCL time tCSH 50 (VDD = 2.7V , Ta = -30 to 85C,Die) Rating Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time SI Data hold time CS-SCL time XCS CS-SCL time tCSH 60 *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard. tSDH tCSS 40 30 SCL Signal Symbol tSCYC tSHW tSLW tSDS Condition Min. 110 60 50 40 Max. ns Units tSDH tCSS 30 20 SCL Signal Symbol tSCYC tSHW tSLW tSDS Condition Min. 100 50 50 30 Max. ns Units
Ver 1.8
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2006/9/18
ST7531
13. RESET TIMING
tRW RST
tR Internal status During reset Reset complete
Fig 43. (VDD = 3.3V , Ta = -30 to 85C,Die) Rating Item Reset time Reset "L" pulse width RST Signal Symbol tR tRW Condition Min. 1 Typ. Max. 1 us us Units
(VDD = 2.7V , Ta = -30 to 85C,Die) Rating Item Reset time Reset "L" pulse width RST Signal Symbol tR tRW Condition Min. 1.5 Typ. Max. 1.5 us us Units
Ver 1.8
74/85
2006/9/18
ST7531
14. THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7531 Series can be connected to either 8080 Series MPUs or to 6800 Series MPUs. Moreover, using the serial interface it is possible to operate the ST7531 series chips with fewer signal lines. The display area can be enlarged by using multiple ST7531 Series chips. When this is done, the chip select signal can be used to select the individual Ics to access. (1) 8080 Series MPUs(8 bit)
VDD VCC A0 XCS
MPU
A0 XCS
VDD IF1
DO to D7 RD WR RST RESET
GND
D0 to D7 E (/RD) R/W (/WR) IF2 RST IF3 VSS VSS
(2) 8080 Series MPUs(16 bit)
VDD VCC A0 XCS
MPU
A0 XCS
VDD IF1
DO to D15 RD WR RST RESET
GND
D0 to D15 E (/RD) R/W (/WR) IF2 RST IF3 VSS VSS
(3) 6800 Series MPUs(8 bit)
VDD VCC A0 XCS
MPU
A0 XCS
VDD IF1
DO to D7 RD WR RST RESET
G ND
D0 to D7 /RD (E) /W R (R/W ) IF2 IF3 RST VSS VSS
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ST7531
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(4) 6800 Series MPUs(16 bit)
VDD VCC A0 XCS
MPU
A0 XCS
VDD IF1
DO to D15 RD WR RST RESET
G ND
D0 to D15 /RD (E) /W R (R/W ) IF2 IF3 RST VSS VSS
(5)
Using the Serial Interface (4-line interface)
V DD o r V SS V CC A0 XCS
MPU
A0 XCS
VDD IF 1
ST7531
P ort 1 P ort 2 RST GND R E SE T
SI SCL RST V SS
IF 2 IF 3
ST7531
V SS
(3) Using the Serial Interface (3-line interface)
VDD VCC VDD IF1 XCS
MPU ST7531
XCS
Port 1 Port 2 RST GND RESET
SI SCL RST VSS
IF2 IF3
VSS
(4) Using the Serial Interface (2-line interface)
VDD VCC VDD IF1
ST7531
MPU
Port 1 Port 2 RST RESET
SI SCL RST VSS
IF2 IF3
GND
VSS
Ver 1.8
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15. Application circuit
Ver 1.8
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Ver 1.8
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Ver 1.8
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Ver 1.8
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Ver 1.8
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Ver 1.8
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ST7531
16. Power Application Note
16.1 Booster Efficiency For COG Applications
Please take care about the ITO resistance, especially for the "Booster Capacitors" (CxP & CxN). The ITO trace will let the booster efficiency decrease a little bit when the loading-current flow through it. As the loading-current become larger, the efficiency will drop more. If the booster power source (VDD2) is lower, the ITO resistance control is more important. Therefore, if the loading is heavy or the VDD2 is lower, the ITO resistance should be kept much lower than the recommended value in this datasheet.
16.2 VLCD Discharge
ST7531 has built-in discharge path on VLCD. The discharge path will discharge the VLCD power when power off. The discharge speed is different under different VLCD voltage. In some application, the discharge speed is not enough. To improve this speed, a discharge resistor is needed. Recommend solution is to add the discharge resistor (about 1M Ohm) between VLCD and VDD2. Please note that the resistor value is different from LCD modules. Actual value should be checked according module display quality.
As the result, the recommended application circuit should introduce the circuit listed below on system FPC (COG applications).
Ver 1.8
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2006/9/18
ST7531
ST7531 Series Specification Revision History
Version 0.0 0.1 Date 2004/4/22 2004/6/08 Preliminary version Add SPRD-B mode color filter Pad Arrangement PAD No. in Pad Center Coordinates BLOCK DIAGRAM SETVOP in Voltage Regulator Circuits Description of Weighting Set, Data Scan Direction, Scroll Set, and Power Control in Commands Add Application note Instruction Setup Flow for Initializing with the built-in Power Supply Circuits The recommended value of regulating capacitance The note for 16-bit interface BLOCK DIAGRAM PIN DESCRIPTION FUNCTIONAL DESCRIPTION Referential Instruction Setup Flow LIMITING VALUES DC CHARACTERISTICS TIMING CHARACTERISTICS RESET TIMING Modify Bias setting value Remove 1.8V timing and modify VDD voltage to 2.4V ~ 3.6V Remove IIC interface Remove RAMRD, RMWIN and RMWOUT command Add some example code and flow chart Add EPINT command Release version Change initial code(Booster must be on first) Modify write EEPROM sequence Add Temperature Gradient Coefficient (Page 1) Add Figure 8.1.1 (Page 39), Figure 8.1.2 (Page 42) 1.3 1.4 1.5 2005/09/15 2005/12/19 2006/01/18 Modify bump height, chip thickness, limiting value..... Add SPRD warning message in page 2 Modify application circuit voltage from 3.6V to 3.3V a. Add Power Application Note.(Page 83) b. Modify Application circuit.(Page 77) c. Modify Voltage Converter circuits.(Page 31) d. Modify Analog circuit set(Oscillator frequency adjustment). (Page 50) e. Modify Initial code flowchart.(Page 56) f. Add Power ON Sequence Note.(Page 55) g. Recommended LCD Vop Voltage.(Page 65) Modify Power Application Note.(Page 83) Description
0.2
2004/09/22
0.3 0.4
2005/01/04 2005/03/01
0.5
2005/04/13
1.0 1.1 1.2
2005/04/29 2005/06/03 2005/08/09
1.6
2006/6/16
1.7
2006/7/6
Ver 1.8
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1.7a 1.8 2006/7/11 2006/9/18 Modify Power Application Note.(Page 83) a. b. Add microprocessor notice item. (page1456) Modify Pad Arrangement.(page 3)
Ver 1.8
85/85
2006/9/18

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